It also includes SmartDebug enhancements, such as the FPGA Hardware Breakpoint (FHB), a capability unique to Microsemi FPGAs. Libero SoC v11.8 provides support for VHDL, Verilog and SystemVerilog to target a broad range of intellectual property (IP) designs without concerns about mixing languages. Libero SoC v11.8 now includes ModelSim Microsemi Pro allowing customers to simulate in mixed language environments as well as 20% runtime improvement in recent versions of the tool. A graphical user interface enables quick identification and debug of problems. Simulation can be performed at all levels: behavioural (pre-synthesis), structural (post-synthesis), and back-annotated, dynamic simulation.
The Libero SoC tool suite includes the Mentor Graphics ModelSim Simulator allowing line by line verification of hardware description language (HDL) code.
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